1. Field of the Invention
The present invention relates to a wiring structure for semiconductor integrated circuits. The present application is based on Japanese Patent Application No. 166316/2000, which is incorporated herein by reference.
2. Background
In a semiconductor device of which high-speed operation is required, a speedup effect of signal wires is also required. However, as is well known, it is important to take measures against a reduction in operating speed in a situation where capacitive coupling occurs between adjacent signal wiring conductors and, in particular, signals in phase opposition to each other flow through adjacent signal wires (hereinafter referred to as crosstalk noise).
A wiring structure for semiconductor integrated circuits will be described with reference to drawings.
FIG. 1 is a wiring layout diagram of Example 1 of the background (using no anti-crosstalk noise measure). Signal wires S1 to S4 are used for output signals from an address buffer or the like and are formed by aluminum wiring. Ordinarily, to increase the degree of integration, signal wires S1 to S4 are formed and arranged so as to minimize their width and the spacing therebetween.
Here, crosstalk noise will be described briefly with reference to FIG. 2 (an equivalent circuit diagram corresponding to the signal wiring in FIG. 1) and FIG. 2 (an F1-F1D cross-sectional view of the signal wire in FIG. 1).
Referring to FIG. 2, well-known inverters INV perform inverting amplification to transfer a change in voltage at an input node to an output node through signal wires S1 to S3. The signal wires S1 to S3 have parasitic resistances and parasitic capacitances. Let each resistance be R. Let the capacitance between each adjacent pair of the signal wires be C1, and the capacitance between each signal wire and the base plate (substrate) (hereinafter referred to as xe2x80x9con-substrate capacitancexe2x80x9d) be C2. The existence of two kinds of capacitances C1 and C2 is apparent from the cross-sectional view in FIG. 3.
The value of C1 and the voltage have direct influence on crosstalk noise.
In general, a delay time ascribable to wiring is expressed by the following equation:
t=xe2x88x92Cxc2x7Rxc2x7ln(Vxe2x80x2/V)xe2x80x83xe2x80x83(Equation A)
where t is a delay time, C is a capacitance value, R is a resistance value, Vxe2x80x2 is a voltage value, V is a voltage value (initial value), and in is a symbol denoting a natural logarithm.
As is apparent from this equation, the delay time is shorter if the capacitance value is smaller.
However, the capacitance value C1 also changes transiently according to the states on the adjacent signal wires (S1 and S2 in this case), and it is difficult to express t only by Equation (A).
When transitions are made on the signal wires S1 and S3 in phase opposition to a transition on the signal wire S2, the capacitance value is effectively maximized.
As a result of a simple speed simulation, it has been confirmed that the delay time when transitions are made on the signal wires S1 and S3 in phase opposition to a transition on the signal wire S2 is 67% longer than the delay time when the potential of each of the signal wires S1 and S3 is fixed at the ground (hereinafter referred to as GND) potential.
Example 2 of the background is an example of a solution of such a problem of Example 1 of the background.
FIG. 4 is a wiring layout diagram of Example 2 of the conventional art (using an anti-crosstalk noise measure). In this example, as shown in FIG. 4, shielding wires D1 to D5 made of the same material and having the same length as the signal wiring conductors S1 to S4 are formed on opposite sides (left and right sides as viewed in the diagram) of each of the signal wiring conductors S1 to S4, and have their potentials fixed at the GND potential. That is, signal wires, shielding wires whose potential is fixed at the GND potential and signal wires of the same structure as the shielding wires are alternately arranged. The GND potential is supplied to the shielding wires from GND pads via aluminum wiring, which is not illustrated.
A description will then be made with reference to FIG. 5 (an F2-F2D cross-sectional view of the signal wire in FIG. 4) and FIG. 6 (a diagram formed by simplifying FIG. 5).
In FIG. 5, C3 represents the capacitance between each of the adjacent signal wire-shielding wire pair, C4 represents the capacitance between each adjacent pair of the signal wires, and C5 and C6 represent on-substrate capacitances.
Then, referring to FIG. 6 which is simplified by considering only the signal wires (the components indicated by the same reference characters in FIGS. 5 and 6 are common components), C3 in the wiring capacitance is expressed as an on substrate capacitance in C3+C5, and C4 is shown in the same manner as in FIG. 5. Ordinarily, C4 is a value much smaller than C3+C5 and can be ignored. As can be understood from the Equation (C) shown above, there is substantially no delay time since C4 can be ignored.
That is, the shielding wire enables high-speed operation through each of the signal wires without influence of changes in voltage on the adjacent signal wires.
Example 1 (FIG. 3) and Example 2 (FIG. 6) of the conventional art will be again referred to and compared.
Since C2 and C3+C5 are substantially equal, it is thought that a cause of occurrence of a significant difference between the delay times depends on the relationship between values of C1 and C4.
It is then assumed that the relationship between the values of C1 and C4 can be represented by the existence/nonexistence of shielding wire and the effect of shielding wire (hereinafter referred to as xe2x80x9cshielding ratioxe2x80x9d) calculated by a simple proportion calculation as shown by the following Equation (B) using the shielding wire length.
Shielding Rate=(Shielding Wire Length/Signal Wire Length)xc3x97100(%)xe2x80x83xe2x80x83(Equation B)
FIG. 7 shows a delay time-shielding rate dependence.
In Example 1 of the background, there is no shielding wire and the shielding rate is expressed as 0.
In Example 2 of the background, each of the signal wire length and the shielding wire length is L and the shielding rate=2L/Lxc3x97100 200% is expressed. The reason for setting the shielding wire length to 2L in obtaining this shielding rate is because shielding wires are provided on the opposite sides of each signal wire (left and right sides as viewed in FIG. 4).
It can be understood from FIG. 7 that if the shielding rate is higher, the delay time is shorter.
In the wiring structure of Example 2, however, if the number of signal wires is n, the wiring area=2n+1 (in the case where shielding wires are provided at the outermost ends) or 2nxe2x88x921 (in the case where no shielding wires are provided at the outermost ends (Example 2 of the background). The wiring area is roughly doubled. Therefore, this method is not suitable for wiring layouts for semiconductor devices of which a high degree of integration is required.
If there is need for a solution optimized in terms of both high-speed performance and degree of integration, an intermediate characteristic between those in Examples 1 and 2 of the background may be required.
It is, therefore, an object of the present invention to provide a wiring method for semiconductor integrated circuits which produces a shielding effect by increasing the wiring area.
In one embodiment of the present invention of a wiring structure for a semiconductor integrated circuit, a shielding wire having the same length as the signal wire and having the ground potential is provided on one of the opposite sides of each of a plurality of signal wires.
In addition, in another embodiment of the present invention of a wiring structure for a semiconductor integrated circuit, a signal wire is bent at a cranking manner, and a shielding wire has the ground potential in an wiring area defined adjacent to the signal wire.
In this case, it is preferred that the shielding wire is formed by being bent according to the cranked portion of the signal wire.
Further, in the invention in each of the two included embodiments, it is preferred that, on a layer in which the signal wire and the shielding wire are formed, a second shielding wire be provided in correspondence with the signal wire, and that the second shielding wire and the shielding wire be connected via a through-hole.
It is also preferred that the ground potential is supplied to the shielding wire via contact from a base plate for the semiconductor integrated circuit.